The serial electrical interface follows the industry-standard serial peripheral interface (SPI), providing a cost-effective non-volatile memory storage solution in systems where pin count must be kept to a minimum. The device is a 1Gb SLC SPI-NAND Flash memory device based on the standard parallel NAND Flash, but  new  command  protocols  and  registers  are  defined  for  SPI operation. It is also an alternative to SPI-NOR, offering superior write performance and cost per bit over SPI-NOR. The command set resembles common SPI-NOR command set, modified to handle NAND-specific functions and new features. New features include user-selectable internal ECC. With internal ECC enabled, ECC code is generated internally when a page is written to the memory array. The ECC code is stored in the spare area of each page. When a page is read to the cache register, the ECC code is calculated again and compared with the stored value. Errors are corrected if necessary. The device either outputs corrected data or returns an ECC error status. The  memory  is  divided  into  blocks  that  can  be  erased independently so it is possible to preserve valid data while old data is erased. The device contains 1024 blocks, composed by 64  pages  consisting  in  two  NAND  structures  of  32  series connected Flash cells. Each page consists 2112-Byte and is further  divided  into  a  2048-Byte  data  storage  area  with  a separate 64-Byte spare area. The 64-Byte area is typically used for memory and error management. The pins serve as the ports for signals. The device has six signal lines plus VCC and ground (GND, VSS). The signal lines are SCK (serial clock), SI (command and data input), SO (response and data output), and control signals CS#, HOLD#, WP#.