M13S128168A-4BG2S

DRAM

M13S128168A-4BG2S

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M13S128168A-4BG2S

Double-data-rate architecture, two data transfers per clock cycle  Bi-directional data strobe (DQS)  Differential clock inputs (CLK and CLK )  DLL aligns DQ and DQS transition with CLK transition  Four bank operation  CAS Latency : 2, 2.5, 3  Burst Type : Sequential and Interleave  Burst Length : 2, 4, 8  All inputs except data & DM are sampled at the rising edge of the system clock (CLK)  Data I/O transitions on both edges of data strobe (DQS)  DQS is edge-aligned with data for READs; center-aligned with data for WRITEs  Data mask (DM) for write masking only  VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V  15.6us refresh interval  Auto & Self refresh  2.5V I/O (SSTL_2 compatible)

DATASHEET

■ SALES INFORMATION

  • ORIGINTAIWAN
  • MANUFACTUREESMT
  • STOCK0
  • DATECODE2022
  • DELIVERY [ STOCK ]Out of stock
  • DELIVERY [ NORMAL ]24W

■ PRODUCTS SPECIFICATION

  • MAKERESMT
  • SORTDDR
  • CAPACITY128Mb
  • ORGANIZATION8Mb X 16
  • SUPPLY [ V ]2.5V
  • REFRESH4K
  • SPEED [ Mhz ]250Mhz
  • PACKAGEBGA-60

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