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JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle z Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z 8 bank operation z CAS Latency : 3, 4, 5, 6, 7 z Additive Latency: 0, 1, 2, 3, 4, 5, 6 z Burst Type : Sequential and Interleave z Burst Length : 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for READ; center-aligned with data for WRITE z Data mask (DM) for write masking only z Off-Chip-Driver (OCD) impedance adjustment z On-Die-Termination for better signal quality z Special function support - 50/ 75/ 150 ohm ODT - High Temperature Self refresh rate enable - Duty Cycle Corrector z Auto & Self refresh z Refresh cycle : - 8192 cycles/64ms (7.8μ s refresh interval) at 0 ℃ ≦ TC ≦ +85 ℃ - 8192 cycles/32ms (3.9μ s refresh interval) at +85 ℃ ＜ TC ≦ +95 ℃ z SSTL_18 interface z If tCK < 1.875ns, the device can not support Write with Auto Precharge function.
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